Datasheet Details
| Part number | MPC9772 |
|---|---|
| Manufacturer | Renesas |
| File Size | 435.53 KB |
| Description | 3.3V 1:12 LVCMOS PLL Clock Generator |
| Datasheet |
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| Part number | MPC9772 |
|---|---|
| Manufacturer | Renesas |
| File Size | 435.53 KB |
| Description | 3.3V 1:12 LVCMOS PLL Clock Generator |
| Datasheet |
|
|
|
|
The MPC9772 utilizes PLL technology to frequency lock its outputs onto an input reference clock.
Normal operation of the MPC9772 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path.