MPC9772 Overview
The MPC9772 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9772 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency.
MPC9772 Key Features
- 1:12 PLL Based Low-Voltage Clock Generator
- 3.3 V Power Supply
- Internal Power-On Reset
- Generates Cock Signals Up to 240 MHz
- Maximum Output Skew of 250 ps
- On-Chip Crystal Oscillator Clock Reference
- Two LVCMOS PLL Reference Clock Inputs
- External PLL Feedback Supports Zero-Delay Capability
- Various Feedback and Output Dividers (See
