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MPC9773 - LVCMOS PLL Clock Generator

General Description

The MPC9773 utilizes PLL technology to frequency lock its outputs onto an input reference clock.

Normal operation of the MPC9773 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path.

Key Features

  • 1:12 PLL based low-voltage clock generator.
  • 3.3 V power supply.
  • Internal power-on reset.
  • Generates clock signals up to 242.5 MHz.
  • Maximum output skew of 250 ps.
  • Differential PECL reference clock input.
  • Two LVCMOS PLL reference clock inputs.
  • External PLL feedback supports zero-delay capability.
  • Various feedback and output dividers (refer to.

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Datasheet Details

Part number MPC9773
Manufacturer Renesas
File Size 524.75 KB
Description LVCMOS PLL Clock Generator
Datasheet download datasheet MPC9773 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
3.3 V 1:12 LVCMOS PLL Clock Generator MPC9773 PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 DATASHEET The MPC9773 is a 3.3 V compatible, 1:12 PLL based clock generator targeted for high-performance low-skew clock distribution in mid-range to highperformance networking, computing, and telecom applications. With output frequencies up to 240 MHz and output skews less than 250 ps the device meets the needs of the most demanding clock applications. Features • 1:12 PLL based low-voltage clock generator • 3.3 V power supply • Internal power-on reset • Generates clock signals up to 242.