R5F10EBAGNA Overview
Datasheet Specifications in this document are tentative and subject to change.
R5F10EBAGNA Key Features
- 1.6 V to 3.6 V operation from a single supply
- Stop (RAM retained): 0.23 µA, (LVD enabled): 0.31
- Halt (RTC + LVD): 0.57 µA
- Snooze: 0.7 mA (UART), 0.6 mA (ADC)
- Operating: 66 µA/MHz
- Delivers 41 DMIPS at maximum operating frequency
- Instruction Execution: 86% of instructions can be
- CISC Architecture (Harvard) with 3-stage pipeline
- MAC: 16 x 16 to 32-bit result in 2 clock cycles
- 16-bit barrel shifter for shift & rotate in 1 clock cycle
