R5F11CCC Datasheet PDF

FEATURES

Ultra-low power consumption technology VDD= 2.4 to 5.5 V HALT mode STOP mode SNOOZE mode RL78 CPU core CISC architecture with 3-stage pipeline Minimum instruction execution time: Can be changed from high speed (0.03125 s: @ 32 MHz operation with high-speed on-chip oscillator or PLL clock)Note to ultra-low speed (1 s: @ 1 MHz operation with highspeed on-chip oscillator or PLL clock) Multiply/divide/multiply & accumulate instructions are supported. Address space: 1 MB General-purpose registers: (8-bit register  8)  4 banks On-chip RAM: 8 KB Note For industrial applications (M; TA = 40 to +125C): 0.04167 s @ 24 MHz operation with high-speed on-chip oscillator or PLL clock Code flash memory Code flash memory: 32 KB Block size: 1 KB Prohibition of block erase and rewriting (security function) On-chip debug function Self-programming (with boot swap function/flash shield window function) Data flash memory Data flash memory: 4 KB Back ground operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory.