Additional preview pages of the R5F11EFAAFP datasheet.
Product details
Features
Ultra-low power consumption technology.
VDD = single power supply voltage of 2.7 to 5.5 V.
HALT mode.
STOP mode.
SNOOZE mode
RL78 CPU core.
CISC architecture with 3-stage pipeline.
Minimum instruction execution time: Can be changed
from high-speed (0.04167 μs: @ 24 MHz operation with high-speed on-chip oscillator) to low-speed (1.0 μs: @1 MHz operation with high-speed on-chip oscillator).
R5F11EFAAFP Datasheet
