R5F12008GNS Datasheet | Renesas

Features Low power consumption technology - VDD = single power supply voltage of 2.4 to 5.5 V - HALT mode - STOP mode RL78 CPU core - CISC architecture with 3-stage pipeline - Minimum instruction execution time: Can be changed from high speed (0.0625 μs: @ 16 MHz operation with high-speed on-chip oscillator) to low speed (1.0 μs: @ 1 MHz operation) - Address space: 1 MB - General-purpose registers: (8-bit register × 8) × 4 banks - On-chip RAM: 1 KB Code flash memory - Code flash memory: 4 to 8 KB - Block size: 1 KB - Only write after erase is possible - On-chip debug function - Self-programming (with no boot swap function/flash shield window function) Data flash memory - Data flash memory: 1 KB - Block size: 512 B - Unit of rewrites: 32 bits - Background operation (BGO) is not supported (instructions cannot be executed from the code flash memory while rewriting the data flash memory) - Number of rewrites: 1,000,000 times (TYP.) - Voltage of rewrites: VDD = 2.4 to 5.5 V High-speed on-chip oscillator - Select from 16 MHz, 8 MHz, 4 MHz, 2 MHz, and 1 MHz R01DS0420EJ0130 Rev.1.30 Aug 9, 2024 - Frequency accuracy ±1.0% (VDD = 2.4 to 5.5 V, TA = - 20 to +85°C) (G: Industrial applications, M: Industrial applications) - Frequency accuracy ±1.5% (VDD = 2.4 to 5.5 V, TA = - 40 to - 20°C) (G: Industrial applications, M: Industrial applications) - Frequency accuracy ±1.5% (VDD = 2.4 to 5.5 V, TA = +85 to +105°C) (G: Industrial applications) - Frequency accuracy ±1.5% (VDD = 2.4 to 5.5 V, TA = +85 to +125°C) (M: Industrial...