Additional preview pages of the R5F1211CGSP datasheet.
R5F1211CGSP Product details
Features
Low power consumption technology.
VDD = single power supply voltage of 2.4 to 5.5 V.
HALT mode.
STOP mode
RL78 CPU core.
CISC architecture with 3-stage pipeline.
Minimum instruction execution time: Can be changed
from high speed (0.0625 μs: @ 16 MHz operation with high-speed on-chip oscillator) to ultra-low speed (30.5 μs: @ 32.768 kHz operation with subsystem clock).
R5F1211CGSP Datasheet
