R5F5110HADLM Overview
Datasheet RX110 Group Renesas MCUs R01DS0202EJ0110 Rev.1.10 Dec 10, 2014 32 MHz 32-bit RX MCUs, 50 DMIPS, up to 128 Kbytes of flash memory, up to 5 ms channels, 12-bit A/D,.
R5F5110HADLM Key Features
- 32-bit RX CPU core
- 32 MHz maximum operating frequency Capable of 50 DMIPS when operating at 32 MHz
- Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations
- Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycl
- Fast interrupt
- CISC Harvard architecture with five-stage pipeline
- Variable-length instruction format, ultra-pact code
- On-chip debugging circuit
- Low power consumption functions
- Operation from a single 1.8 to 3.6 V supply