R5F51136ADLJ
Features
- 32-bit RX CPU core
- 32 MHz maximum operating frequency Capable of 50 DMIPS when operating at 32 MHz
- Accumulator handles 64-bit results (for a single instruction) from 32bit × 32-bit operations
- Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle)
- Fast interrupt
- CISC Harvard architecture with five-stage pipeline
- Variable-length instruction format, ultra-pact code
- On-chip debugging circuit
- Low power consumption functions
- Operation from a single 1.8 to 3.6 V supply
- Three low power consumption modes
- Low power timer (LPT) that operates during the software standby state
- Supply current
High-speed operating mode: 0.11 m A/MHz Software standby mode: 0.44 µA
- Recovery time from software standby mode: 4.8 µs
- On-chip flash memory for code, no wait states
- Operation at 32 MHz, read cycle of 31.25 ns
- No wait states for reading at full CPU speed
- 128 to 512 Kbyte capacities
- Programmable at...
