R5F51138ADLJ Overview
Datasheet RX113 Group Renesas MCUs 32 MHz, 32-bit RX MCUs, 50 DMIPS, up to 512 Kbytes of flash memory, R01DS0216EJ0120 Rev.1.20 Sep 07, 2020 USB 2.0 full-speed host/function/OTG, up to 12 ms channels, serial sound interface, LCD controller/driver, capacitive.
R5F51138ADLJ Key Features
- 32-bit RX CPU core
- 32 MHz maximum operating frequency Capable of 50 DMIPS when operating at 32 MHz
- Accumulator handles 64-bit results (for a single instruction) from 32bit × 32-bit operations
- Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycl
- Fast interrupt
- CISC Harvard architecture with five-stage pipeline
- Variable-length instruction format, ultra-pact code
- On-chip debugging circuit
- Low power consumption functions
- Operation from a single 1.8 to 3.6 V supply