R5F51306BDFL
Features
- 32-bit RX CPU core
- Max. operating frequency: 32 MHz Capable of 50 DMIPS in operation at 32 MHz
- Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations
- Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle)
- Fast interrupt
- CISC Harvard architecture with 5-stage pipeline
- Variable-length instructions, ultra-pact code
- On-chip debugging circuit
- Low power design and architecture
- Operation from a single 1.8-V to 5.5-V supply
- Three low power consumption modes
- Low power timer (LPT) that operates during the software standby state
- Supply current High-speed operating mode: 96 µA/MHz Supply current in software standby mode: 0.37 µA
- Recovery time from software standby mode: 4.8 µs
- On-chip flash memory for code, no wait states
- 64 K/128 K/256 K/383 K/512 Kbytes
- Operation at 32 MHz, read cycle of 31.25 ns
- No wait states for reading at full CPU speed
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