R5F51306BGFL Datasheet | Renesas

Features - 32-bit RX CPU core - Max. operating frequency: 32 MHz Capable of 50 DMIPS in operation at 32 MHz - Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations - Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle) - Fast interrupt - CISC Harvard architecture with 5-stage pipeline - Variable-length instructions, ultra-pact code - On-chip debugging circuit - Low power design and architecture - Operation from a single 1.8-V to 5.5-V supply - Three low power consumption modes - Low power timer (LPT) that operates during the software standby state - Supply current High-speed operating mode: 96 µA/MHz Supply current in software standby mode: 0.37 µA - Recovery time from software standby mode: 4.8 µs - On-chip flash memory for code, no wait states - 64 K/128 K/256 K/383 K/512 Kbytes - Operation at 32 MHz, read cycle of 31.25 ns - No wait states for reading at full CPU speed - Programmable at 1.8 V - For instructions and operands - On-chip data flash memory - 8 Kbytes (1,000,000 program/erase cycles (typ.)) - BGO (Background Operation) - On-chip SRAM, no wait states - 10 K/16 K/32 K/48 Kbytes size capacities - DTC - Four transfer modes - Transfer can be set for each interrupt source. - ELC - Module operation can be initiated by event signals without using interrupts. - Linked operation between modules is possible while the CPU is sleeping. - Reset and supply management - Eight types of reset, including the power-on reset (POR) - Low voltage detection (LVD) with voltage settings - Clock functions - External clock input frequency: Up to 20 MHz - Main clock oscillator frequency: 1 to 20 MHz - Sub clock oscillator frequency: 32.768 k Hz - PLL circuit input: 4 MHz to 8...