R5F521A6BDFP Datasheet Text
Datasheet
RX21A Group
Renesas MCUs
50-MHz 32-bit RX MCUs, 78 DMIPS, 24-bit ∆Σ A/D Converter, up to 512-KB flash memory, IrDA, 10-bit A/D, 10-bit D/A, DEU, ELC, MPC, RTC; up to 9 ms interfaces
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
Features
- 32-bit RX CPU core
- Max. operating frequency: 50 MHz Capable of 78 DMIPS in operation at 50 MHz
- Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations
- Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle)
- Fast interrupt
- CISC Harvard architecture with 5-stage pipeline
- Variable-length instructions, ultra-pact code
- Memory protection unit
- On-chip debugging circuit
- Low power design and architecture
- Operation from a single 1.8-V to 3.6-V supply (2.7 V to 3.6 V for the ΔΣ A/D converter operating voltage)
- Deep software standby mode with RTC remaining usable
- Four low power modes
- 24-bit ∆Σ A/D Converter
- SNDR = 85dB
- Seven ΔΣ converter units available. Seven channels can be operated simultaneously or independently.
- Up to x 64 PGA gain for differential input
- On-chip flash memory for code, no wait states
- 50-MHz operation, 20-ns read cycle
- No wait states for reading at full CPU speed
- 256-K to 512-Kbyte capacities
- User code programmable via the SCI
- Programmable at 1.8 V...