R5F52205BDFL Overview
Preliminary Datasheet Specifications in this document are tentative and subject to change. RX220 Group Renesas MCUs 32-MHz 32-bit RX MCUs, 49 DMIPS, up to 256-KB flash memory, 12-bit A/D, ELC, MPC, RTC, up to 7 ms channels; incorporating functions for IEC60730 pliance R01DS0130EJ0051 Rev.0.51 May 24, 2012.
R5F52205BDFL Key Features
- 32-bit RX CPU core
- Max. operating frequency: 32 MHz
- Capable of 49 DMIPS in operation at 32 MHz
- Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations
- Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle)
- Fast interrupt
- CISC Harvard architecture with 5-stage pipeline
- Variable-length instructions, ultra-pact code
- On-chip debugging circuit
- Low-power design and architecture