Datasheet Details
| Part number | R5F52206BDFP |
|---|---|
| Manufacturer | Renesas |
| File Size | 1.00 MB |
| Description | 32-MHz 32-bit RX MCUs |
| Datasheet |
 R5F52206BDFP Datasheet
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General Description
Maximum operating frequency: 32 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One
Key Features
- 32-bit RX CPU core.
- Max. operating frequency: 32 MHz.
- Capable of 49 DMIPS in operation at 32 MHz.
- Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations.
- Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle).
- Fast interrupt.
- CISC Harvard architecture with 5-stage pipeline.
- Variable-length instructions, ultra-compact code.
- On-chip debugging circuit.