R5F523T5ADFL - MCU

Product Overview

Renesas

Datasheet Details

Part number	R5F523T5ADFL
Manufacturer	Renesas
File Size	1.02 MB
Description	MCU
Datasheet	R5F523T5ADFL Datasheet
Additional preview pages of the R5F523T5ADFL datasheet.

Product details

Description

CPU CPU Maximum operating frequency: 40 MHz 32-bit RX CPU (RX v2) Minimum instruction execution time: One instruction per clock cycle Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Ten 32-bit registers Accumulator: Two 72-bit registers Basic instructions: 75 Variable-length instruction format Floating-point instructions: 11 DSP instructions: 23 Addressing modes: 11 Data arrangement Instr

Features

32-bit RX CPU core.
Max. operating frequency: 40 MHz Capable of 65.6 DMIPS in operation at 40 MHz.
Enhanced DSP: 32-bit multiply-accumulate and 16-bit multiply-subtract instructions supported.
Built-in FPU: 32-bit single-precision floating point (compliant to IEEE754).
Divider (fastest instruction execution takes two CPU clock cycles).
Fast interrupt.
CISC Harvard architecture with 5-stage pipeline.
Variable-length instructions, ultra-compact code.
O.

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Published: Aug 12, 2020 |