R5F5631JDGFB Datasheet | Renesas

Features RX63N Group, RX631 Group Renesas MCUs R01DS0098EJ0180 100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, up to 2-MB flash memory, various munications interfaces including Ethernet MAC, Rev.1.80 May 13, 2014 full-speed USB 2.0 host/function/OTG interface, CAN, 10- & 12-bit A/D converters, RTC Features RX63N Group products incorporate an Ethernet controller while RX631 Group products do not. - 32-bit RX CPU core - Max. operating frequency: 100 MHz - Capable of 165 DMIPS in operation at 100 MHz - Single precision 32-bit IEEE-754 floating point - Two types of multiply-and-accumulation unit (between memories and between registers) - 32-bit multiplier (fastest instruction execution takes one CPU clock cycle) - Divider (fastest instruction execution takes two CPU clock cycles) - Fast interrupt - CISC Harvard architecture with 5-stage pipeline - Variable-length instructions: Ultra-pact code - Supports the memory protection unit (MPU) - JTAG and FINE (two-line) debugging interfaces - Low-power design and architecture - Operation from a single 2.7- to 3.6-V supply - Low power consumption: A product that supports all peripheral functions draws only 500 μA/MHz. - RTC is capable of operation from a dedicated power supply (min. operating voltage: 2.3 V). - Four low-power modes - On-chip main flash memory, no wait states - Supports ROM-less versions and versions with up to 2 Mbytes of ROM (ROMless/256 Kbytes/384 Kbytes/512 Kbytes: RX631 Group only) - 100-MHz operation, 10-ns read cycle (no wait states) - 768-Kbyte to 2-Mbyte capacities - User code is programmable by on-board or off-board...