R7F100GMJ Datasheet | Renesas

Features Ultra-low power consumption technology - VDD = single power supply voltage of 1.6 to 5.5 V - HALT mode - STOP mode High-speed wakeup from the STOP mode is possible. - SNOOZE mode RL78 CPU core - CISC architecture with 3-stage pipeline - Minimum instruction execution time: Can be changed from high speed (0.03125 µs @ 32 MHz operation with the high-speed on-chip oscillator clock) to ultra-low speed (30.5 µs @ 32.768 k Hz operation with the subsystem clock) - Multiply/divide/multiply & accumulate instructions are supported. - Address space: 1 MB - General-purpose registers: (8-bit register × 8) × 4 banks - On-chip RAM: 12 to 48 KB Code flash memory - Code flash memory: 96 to 768 KB - Block size: 2 KB - Prohibition of block erase and rewriting (security function) - On-chip debugging - Self-programming (with boot swapping and flash shield window) Data flash memory - Data flash memory: 8 KB - Background operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory. - Number of rewrites: 1,000,000 times (typ.) High-speed on-chip oscillator - Select from 32 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, or 1 MHz - High accuracy: ±1.0% (VDD = 1.8 to 5.5 V, TA = -20 to +85°C) Middle-speed on-chip oscillator - Select from 4 MHz, 2 MHz, or 1 MHz (with adjustability) Low-speed on-chip oscillator - 32.768 k Hz (typ.) (with adjustability) Operating ambient temperature - TA = -40 to +85°C (2D: Consumer applications) - TA = -40 to +105°C (3C: Industrial applications) Power management and reset function - On-chip power-on-reset (POR)...