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X28C256 - Byte Alterable EEPROM

Features

  • DATA polling and Toggle bit polling, two methods of providing early end of write detection. The X28HC256 also supports the JEDEC standard software data protection feature for protecting against inadvertent writes during power-up and power-down. Endurance for the X28HC256 is specified as a minimum 100,000 write cycles per byte and an inherent data retention of 100 years.

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Datasheet Details

Part number X28C256
Manufacturer Renesas
File Size 867.23 KB
Description Byte Alterable EEPROM
Datasheet download datasheet X28C256 Datasheet
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Full PDF Text Transcription

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X28HC256 256k, 32k x 8-Bit, 5V, Byte Alterable EEPROM The X28HC256 is a second generation high performance CMOS 32k x 8 EEPROM. It is fabricated with Intersil’s proprietary, textured poly floating gate technology, providing a highly reliable 5V only nonvolatile memory. The X28HC256 supports a 128-byte page write operation, effectively providing a 24µs/byte write cycle, and enabling the entire memory to be typically rewritten in less than 0.8s. The X28HC256 also features DATA polling and Toggle bit polling, two methods of providing early end of write detection. The X28HC256 also supports the JEDEC standard software data protection feature for protecting against inadvertent writes during power-up and power-down.
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