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uPD44325362B - 36M-BIT QDR II SRAM

Download the uPD44325362B datasheet PDF. This datasheet also covers the uPD44325092B variant, as both devices belong to the same 36m-bit qdr ii sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The μPD44325092B is a 4,194,304-word by 9-bit, the μPD44325182B is a 2,097,152-word by 18-bit and the μPD44325362B is a 1,048,576-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

Key Features

  • 1.8 ± 0.1 V power supply.
  • 165-pin.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (uPD44325092B-Renesas.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
UPD44325362 36M-BIT QDRII SRAM NEC
UPD44325364 36M-BIT QDRII SRAM NEC
UPD44325082 36M-BIT QDRII SRAM NEC
UPD44325084 36M-BIT QDRII SRAM NEC
UPD44325092 36M-BIT QDRII SRAM NEC

Other Datasheets by Renesas

Part Number Description
uPD44325092B 36M-BIT QDR II SRAM
uPD44325182B 36M-BIT QDR II SRAM
uPD46184095B 18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION
uPD46184182B 18M-BIT DDR II SRAM 2-WORD BURST OPERATION
uPD46184184B 18M-BIT DDR II SRAM 4-WORD BURST OPERATION

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
μPD44325092B μPD44325182B μPD44325362B Datasheet 36M-BIT QDRTM II SRAM 2-WORD BURST OPERATION R10DS0038EJ0200 Rev.2.00 August 11, 2011 Description The μPD44325092B is a 4,194,304-word by 9-bit, the μPD44325182B is a 2,097,152-word by 18-bit and the μPD44325362B is a 1,048,576-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The μPD44325092B, μPD44325182B and μPD44325362B integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K#. These products are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration.