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uPD46365362B - 36M-BIT QDR II SRAM 2-WORD BURST OPERATION

Download the uPD46365362B datasheet PDF. This datasheet also covers the uPD46365092B variant, as both devices belong to the same 36m-bit qdr ii sram 2-word burst operation family and are provided as variant models within a single manufacturer datasheet.

General Description

The μPD46365092B is a 4,194,304-word by 9-bit, the μPD46365182B is a 2,097,152-word by 18-bit and the μPD46365362B is a 1,048,576-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

Key Features

  • 1.8 ± 0.1 V power supply.
  • 165-pin.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (uPD46365092B-Renesas.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number uPD46365362B
Manufacturer Renesas
File Size 584.33 KB
Description 36M-BIT QDR II SRAM 2-WORD BURST OPERATION
Datasheet download datasheet uPD46365362B Datasheet

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Other Datasheets by Renesas

Part Number Description
uPD46365364B 36M-BIT QDR II SRAM 4-WORD BURST OPERATION
uPD46365084B 36M-BIT QDR II SRAM 4-WORD BURST OPERATION
uPD46365092B 36M-BIT QDR II SRAM 2-WORD BURST OPERATION
uPD46365094B 36M-BIT QDR II SRAM 4-WORD BURST OPERATION
uPD46365182B 36M-BIT QDR II SRAM 2-WORD BURST OPERATION

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
μPD46365092B μPD46365182B μPD46365362B Datasheet 36M-BIT QDRTM II SRAM 2-WORD BURST OPERATION R10DS0089EJ0400 Rev.4.00 Nov 09, 2012 Description The μPD46365092B is a 4,194,304-word by 9-bit, the μPD46365182B is a 2,097,152-word by 18-bit and the μPD46365362B is a 1,048,576-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The μPD46365092B, μPD46365182B and μPD46365362B integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K#. These products are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration.