PX5 Overview
PX5 Datasheet Rev 1.1 Rockchip PX5 Datasheet Revision 1.1 July. 2016 Copyright 2016 @Fuzhou Rockchip Electronics Co., Ltd. 1 PX5 Datasheet Rev 1.1 Chapter 1 Introduction 1.1 Overview PX5 is a low power, high performance processor for in-vehicle infotainment system, support Android based on the ARM Cortex architecture,, and integrates octa-core Cortex-A53 with separately NEON coprocessor.
PX5 Key Features
- Octa-core ARM Cortex-A53 MP Core processor, a high-performance, low-power and cached application processor
- Two CPU clusters, with four CPU core for each cluster, One cluster is optimized for high-performance(big cluster) and th
- Full implementation of the ARM architecture v8-A instruction set, ARM Neon Advanced SIMD (single instruction, multiple d
- ARMv8 Cryptography Extensions
- In-order pipeline with symmetric dual-issue of most instructions
- Harvard Level 1 (L1) memory system with a Memory Management Unit (MMU)
- Level 2 (L2) memory system providing cluster memory coherency, including an L2 cache
- Include VFP v3 hardware to support single and double-precision add, subtract, divide
- SCU ensures memory coherency between the four CPUs for each cluster
- CCI400 ensures the memory coherency between the two clusters
