PX5
Key Features
- 2.1 Processor
- Octa-core ARM Cortex-A53 MP Core processor, a high-performance, low-power and cached application processor
- Two CPU clusters, with four CPU core for each cluster, One cluster is optimized for high-performance(big cluster) and the other is optimized for low power(little cluster)
- Full implementation of the ARM architecture v8-A instruction set, ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
- ARMv8 Cryptography Extensions
- In-order pipeline with symmetric dual-issue of most instructions.
- Harvard Level 1 (L1) memory system with a Memory Management Unit (MMU).
- Level 2 (L2) memory system providing cluster memory coherency, including an L2 cache.
- Include VFP v3 hardware to support single and double-precision add, subtract, divide, multiply and accumulate, and square root operations
- SCU ensures memory coherency between the four CPUs for each cluster
