RK3588J
Description
CPU frequency and pin information 1.0 Initial release Copyright © 2023, Rockchip Electronics Co., Ltd. 1 RK3588J Datasheet Rev 1.1 Chapter 1 Introduction.
Key Features
- DSU (DynamIQ Shared Unit) prises the L3 memory system, control logic, and external interfaces to support a DynamIQ cluster
- ARMv8 Cryptography Extensions
- Trustzone technology support
- Integrated 64KB L1 instruction cache, 64KB L1 data cache and 512KB L2 cache for each Cortex-A76
- Integrated 32KB L1 instruction cache, 32KB L1 data cache and 128KB L2 cache for each Cortex-A55
- Quad-core Cortex-A76 and Quad-core Cortex-A55 share 3MB L3 cache
- PD_CPU_0: 1st Cortex-A55 + Neon + FPU + L1/L2 I/D Cache
- PD_CPU_1: 2nd Cortex-A55 + Neon + FPU + L1/L2 I/D Cache
- PD_CPU_2: 3rd Cortex-A55 + Neon + FPU + L1/L2 I/D Cache
- PD_CPU_3: 4th Cortex-A55 + Neon + FPU + L1/L2 I/D Cache
