K7A161830B Datasheet PDF - SAMSUNG ELECTRONICS 512Kx36 & 1Mx18 Synchronous SRAM Specs

K7A161830B - 512Kx36 & 1Mx18 Synchronous SRAM

This page provides the datasheet information for the K7A161830B, a member of the K7A163630B 512Kx36 & 1Mx18 Synchronous SRAM family.

Datasheet Summary

Description

The K7A163630B and K7A161830B are 18,874,368-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System.

Features

Synchronous Operation.
2 Stage Pipelined operation with 4 Burst.
On-Chip Address Counter.
Self-Timed Write Cycle.
On-Chip Address and Control Registers.
VDD= 2.5 or 3.3V +/- 5% Power Supply.
5V Tolerant Inputs Except I/O Pins.
Byte Writable Function.
Global Write Enable Controls a full bus-width write.
Power Down State via ZZ Signal.
LBO Pin allows a choice of either a interleaved burst.

Datasheet Details

Part number	K7A161830B
Manufacturer	SAMSUNG ELECTRONICS
File Size	400.32 KB
Description	512Kx36 & 1Mx18 Synchronous SRAM
Datasheet	K7A161830B Datasheet
Additional preview pages of the K7A161830B datasheet.

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Full PDF Text Transcription

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K7A163630B K7A161830B www.DataSheet4U.com 512Kx36 & 1Mx18 Synchronous SRAM 18Mb B-die Sync. SRAM Specification 100TQFP with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2.

Published: Jun 12, 2010 |