M368L6523CUS Overview
Key Features
- VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR333
- VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
- Double-data-rate architecture; two data transfers per clock cycle
- Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
- Differential clock inputs(CK and CK)
- DLL aligns DQ and DQS transition with CK transition
- Programmable Read latency : DDR333(2.5 Clock), DDR400(3 Clock)
