DESCRIPTION
FINAL FEATURES
DATASHEET ACS8530 SETS The device supports Free-run, Locked and Holdover modes. It also supports all three types of reference clock source: recovered line clock, PDH network, and node synchronization. The ACS8530 generates independent SEC and BITS clocks, an 8 kHz Frame Synchronization clock and a 2 kHz Multi-Frame Synchronization clock. Two ACS8530 devices can be used together in a Master/ Slave configuration mode allowing system protection against a single ACS8530 failure. A microprocessor port is incorporated, providing access to the configuration and status registers for device setup and monitoring. The ACS8530 supports IEEE 1149.1[5] JTAG boundary scan. Block Diagram Suitable for Stratum 2, 3E, 3, 4E and 4 and SONET Minimum Clock (SMC) or SONET/SDH Equipment Clock (SEC) applications (to Telcordia 1244-CORE[19] Stratum 3E, and GR-253[17], and ITU-T G.812[10] Type III and G.813[11] specifications) Accepts 14 individual input reference clocks, all with...