74AC4520 Datasheet | SGS-THOMSON

.Data Sheet.co.kr M54/M74HC4518 M54/M74HC4520 HC4518 DUAL DECADE COUNTER HC4520 DUAL 4 BIT BINARY COUNTER - . . . HIGH SPEED f MAX = 55 MHz (TYP.) at VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 m A (MIN.) BALANCED PROPAGATION DELAYS t PLH = t PHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION PATIBLE WITH 4520B/4518B B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HCXXXXF1R M74HCXXXXM1R M74HCXXXXB1R M74HCXXXXC1R PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC4518/4520 are high speed CMOS DUAL 4 BIT BINARY COUNTERS fabricated in sili2 con gate C MOS technology. They have the same high speed performance of LSTTL bined with true CMOS low power consumption. They consists of two identical internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable Clock and ENABLE inputs for incrementing on either the positive-going or negative-going transition. For single-unit operation the ENABLE input is maintained ”high” and the counter advances on each positive-going transition of the CLOCK. The counters are cleared by high levels on their clear lines. The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the clock input of the latter is held permanently low. All inputs are equipped with protection circuits against static discharge and transient excess voltage. March 1993 NC = No Internal Connection 1/13 Datasheet pdf - http://..net/ .Data Sheet.co.kr M54/M74HC4518/4520 LOGIC DIAGRAM (1/2 HC4518) LOGIC DIAGRAM (1/2 HC4520) 2/13 Datasheet pdf - http://..net/ .Data Sheet.co.kr M54/M74HC4518/4520 TIMING CHART (HC4518) TIMING CHART (HC4520) 3/13 Datasheet...