M4116 Datasheet | SGS

I.os INTEGRATED CIRCUIT ~ - t '16384-BIT DYNAMIC RANDOM ACCESS MEMORY M 4118 PRELIMINARY DATA RECOGNIZED INDUSTRY STANDARD 16-PIN CONFIGURATION 150ns ACCESS TIME, 320ns CYCLE (M 4116-2) 200ns ACCESS TIME, 375ns CYCLE (M 4116-3) 250ns ACCESS TIME, 410ns CYCLE (M 4116-4) ± 10% TOLERANCE ON ALL POWER SUPPLIES (+ 12V, ±5V) LOW POWER: 462 m W ACTIVE, 20 m W STANDBY (MAX) - ~~. OUTPUT DATA CONTROLLED BY CAS AND UNLATCHED AT END OF CYCLE l WO DIMENSIONAL CHIP SELECTION AND EXTENDED PAGE BOUNDARY ALLOW MON I/O CAPABILITY USING "EARLY WRITE" OPERATION READ-MODIFY-WRITE, RAS-ONLY REFRESH, AND PAGE-MODE CAPABILITY ~. ALL INPUTS TTL PATIBLE, LOW CAPACITANCE, AND PROTECTED AGAINST STATIC >. CHARGE ~ 12B REFRESH CYCLES :. MOSTEK 4116 PIN TO PIN REPLACEMENT '.- ECL PATIBLE ON Vee POWER SUPPLY (-5.7V) ~the M 4116 is a new generation MOS dynamic random access memory circuit organized as 16384 words :.'by 1 bit. The technology used to fabricate the M 4116 is double-poly N-channel silicon gate. - This process, coupled with the use of a single transistor dynamic storage cell, provides the maximum posl$ible circuit density and reliability, while maintaining high performance capability. The use of dynamic ,'circuitry through-out, including sense amplifiers, assures that power dissipation is minimized without ~ny sacrifice in speed or operating margin. l Multiplexed address inputs permits the M 4116 to be packaged in a standard 16-pin DIP. The device is tavailable in 16-lead dual in-line ceramic package. ABSOLUTE MAXIMUM RATINGS- Voltage on any pin relative to Vee Voltage on VDD , Vee supplies relative to Vss > Vee-Vss (VDD-VSS OV) Top Operating temperature Tstg Storage temperature for ceramic package . for plastic package Short circuit output current Ptot Total power dissipation -0.5 to +20 -1 to+15 V o to...