COM90C66 Datasheet | SMSC

FEATURES - - - - - - - - - ARCNET LAN Controller/Transceiver/ Support Logic/Dual-Port RAM Integrates SMSC 90C65 with 16-Bit Data Bus, Dual-Port RAM, and Enhanced Diagnostics Circuitry Includes IBM® PC/AT® Bus Interface Circuitry Supports 8- and 16-Bit Data Buses Full 2K x 8 On-Chip Dual-Port Buffer RAM Zero Wait State Arbitration for Most AT Buses SMSC 90C26 Software patible mand Chaining Enhances Performance Supports Memory Mapped and Sequential I/O Mapped Access to the Internal RAM Buffer - - - - - - - - - - patible with the SMSC HYC9058/68/ 88 (COAX and Twisted Pair Drivers) Token Passing Protocol with Self Reconfiguration Detection Variable Data Length Packets 16 Bits CRC Check/Generation Includes Address Decoding Circuitry for On Chip RAM, PROM and I/O Supports up to 255 Nodes Contains Software Accessible Node ID Register patible with Various Topologies (Star, Tree, Bus, ...) On-Board Crystal Oscillator and Reset Circuitry Low Power CMOS, Single +5V Supply GENERAL DESCRIPTION The SMSC 90C66 is a special purpose munications controller for interconnecting processors and intelligent peripherals using the ARCNET Local Area Network. The 90C66 is unique in that it integrates the core ARCNET logic found in Standard Microsystems' original 90C26 and 90C32 with an on-chip 2K x 8 RAM, as well as the 16-bit data bus interface for the IBM PC/AT. Because of the inclusion of the RAM buffer in the 90C66, a plete ARCNET node can be implemented with only one or two additional ICs (8- or 16-bit applications, respectively) and a media driver circuit. The ARCNET core remains functionally untouched, eliminating validation and patibility concerns. The enhancements exist in the integration and the performance of the 1 device. Maximum integration has been achieved by including the 2K x 8 RAM buffer on the chip, providing the immediate benefits of a lower device pin count and less board ponents. The performance is enhanced in four ways: a 16-bit data bus for operation with the IBM...