SPARC STP1030
The STP1030, UltraSPARC-I, is a high-performance, highly-integrated superscalar processor implementing the SPARC V9 64-bit RISC architecture. The STP1030 is capable of sustaining the execution of up to four instructions per cycle even in the presence of conditional branches and cache misses. This sustained performance is supported by a decoupled Prefetch and Dispatch Unit with Instruction Buffer to feed the Execution Unit.| Part No. | STP1030 |
|---|---|
| Datasheet | STP1030 Download |
| Manufacturer | SPARC |
| Description | High-Performance 64-Bit RISC Processor |
| Buy | Stock & Price |
FEATURES
:● SPARC V9 Architecture Compliant
● Binary Compatible with all SPARC Application code
● VISual (Multimedia Capable) Instruction Set
● Multi-Processing Support - Glueless 4-processor connection with minimum latency - Snooping or Directory Based Protocol Support
● 4-way SuperScalar Design with 9 execution units - 4 Integer Execution Units - 3 Floating-point Execution Units - 2 Graphics Execution Units
● Selectable Little or Big Endian Byte Ordering
● 64-Bit Address Pointers
● 16KByte Non-blocking Data Cache
● 16KByte Instruction Cache - In-Cache 2-bit Branch Prediction - Single Cycle Branch Following
● Integrated 2nd Level Cache Controller - Supports .5-4MBytes Cache Sizes - Sustained throughput of 1 load/cycle - 2.6Gbyte/sec Processor-Cache bandwidth
● Block Load/Store Instructions - 1.3GByte/sec processor-memory bandwidth - 600 MByte/sec Sustained Processor-Memory Transfers
● Ease of Use - JTAG Boundary scan - Performance Instrumentation
● Technology/packaging - 0.5um 4-layer...
