STP1030 Datasheet | SPARC

SPARC Technology Business Preliminary May 1995 DATA SHEET Ultra SPARC-I High-Performance 64-Bit RISC Processor INTRODUCTION The STP1030, Ultra SPARC-I, is a high-performance, highly-integrated superscalar processor implementing the SPARC V9 64-bit RISC architecture. The STP1030 is capable of sustaining the execution of up to four instructions per cycle even in the presence of conditional branches and cache misses. This sustained performance is supported by a decoupled Prefetch and Dispatch Unit with Instruction Buffer to feed the Execution Unit. On the output side of the Execution Unit, Load and Store buffers pletely decouple pipeline execution from data cache misses. Instructions predicted to be executed are issued in program order to multiple functional units, execute in parallel and can plete out of order. In order to further increase the number of instructions executed per cycle, instructions from different blocks (e.g. instructions before and after a conditional branch) can be issued in the same group. The STP1030 supports 2D, 3D graphics, image processing, video pression and depression and video effects through the sophisticated VISual Instruction Set. This instruction set supports high levels of multimedia performance including real-time H.261 video pression/depression and 2 streams of MPEG-2 depression at full broadcast quality with no additional hardware support. Features : - SPARC V9 Architecture pliant - Binary patible with all SPARC Application code - VISual (Multimedia Capable) Instruction Set - Multi-Processing Support - Glueless 4-processor connection with minimum latency - Snooping or Directory Based Protocol Support - 4-way Super Scalar Design with 9 execution units - 4 Integer Execution Units - 3 Floating-point Execution Units - 2 Graphics Execution Units - Selectable Little or Big Endian Byte Ordering - 64-Bit Address Pointers - 16KByte Non-blocking Data Cache - 16KByte Instruction Cache - In-Cache 2-bit...