SST SST49LF016C
The SST49LF016C flash memory device is designed to interface with host controllers (chipsets) that support a lowpin-count (LPC) interface for system firmware applications. The LPC interface operates with 5 signal pins versus 28 pins of a 8-bit parallel flash memory. This frees up pins on the ASIC host controller resulting in lower ASIC costs and a reduction in overall system costs due to simplified signal routing.FEATURES
:● Operational Clock Frequency – 33 MHz – 66 MHz
● Organized as 2M x8
● Conforms to LPC Interface Specification v1.1 – Support Multi-Byte Firmware Memory Read/ Write Cycles
● Single 3.0-3.6V Read and Write Operations
● LPC Mode – 5-signal LPC bus interface for both in-system and factory programming using programmer equipment – Multi-Byte Read data transfer rate 15.6 MB/s @ 33 MHz PCI clock and 31.2 MB/s @ 66 MHz clock - Firmware Memory Read cycle supporting 1, 2, 4, 16, and 128 Byte Read - Firmware Memory Write cycle supporting 1, 2, and 4 Byte Write – 33 MHz/66 MHz clock frequency operation – WP#/AAI and TBL# pins provide hardware Write protect for entire chip and/or top Boot Block – Block Locking Registers for individual block ReadLock, Write-Lock, and Lock-Down protection – 5 GPI pins for system design flexibility – 4 ID pins for multi-chip selection – Multi-Byte capability registers (read-only registers) – Status register for End-of-Write detection – Program-/Erase-Suspend...