27256 Datasheet | STMicroelectronics

M74HC51 DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE s s s s s s s HIGH SPEED: t PD = 11ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4m A (MIN) BALANCED PROPAGATION DELAYS: t PLH ≅ t PHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION PATIBLE WITH 74 SERIES 51 TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC51B1R M74HC51M1R T&R M74HC51RM13TR M74HC51TTR DESCRIPTION The M74HC51 is an high speed CMOS DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE fabricated with silicon gate C2MOS technology. It contains a 2-WIDE 2-INPUT AND/OR INVERT GATE and a 2-WIDE 3-INPUT AND/OR INVERT GATE. The internal circuit is posed of 3 stages (2 INPUT) or 5 stages (3 INPUT) including buffer output, which enables high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/9 M74HC51 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 12, 13, 9, 10, 11 2, 3, 4, 5 8, 6 7 14 SYMBOL 1A to 1F 2A to 2D 1Y to 2Y GND VCC NAME AND FUNCTION Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE 1A H X 1B 1C 1D 1E 1F X H 1Y L L H H H X X X X H H ALL OTHER BINATIONS TRUTH TABLE 2A H X 2B 2C 2D 2Y L L H H X X X H H ALL OTHER BINATIONS X : Don’t...