M36L0R7050 Datasheet | STMicroelectronics

FEATURES SUMMARY MULTI-CHIP PACKAGE - 1 die of 128 Mbit (8Mb x16, Multiple Bank, Multi-level, Burst) Flash Memory - 1 die of 32 Mbit (2Mb x16) Asynchronous Pseudo SRAM - SUPPLY VOLTAGE - VDDF = VDDP = VDDQ = 1.7 to 1.95V - VPPF = 9V for fast program (12V tolerant) - ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Device Code (Top Flash Configuration) M36L0R7050T0: 88C4h - Device Code (Bottom Flash Configuration) M36L0R7050B0: 88C5h - PACKAGE - pliant with Lead-Free Soldering Processes - Lead-Free Versions FLASH MEMORY - SYNCHRONOUS / ASYNCHRONOUS READ - Synchronous Burst Read mode: 54MHz - Asynchronous Page Read mode - Random Access: 85ns - SYNCHRONOUS BURST READ SUSPEND - PROGRAMMING TIME - 10µs typical Word program time using Buffer Program - MEMORY ORGANIZATION - Multiple Bank Memory Array: 8 Mbit Banks - Parameter Blocks (Top or Bottom location) - DUAL OPERATIONS - program/erase in one Bank while read in others - No delay between read and write operations - SECURITY - 64 bit unique device number - 2112 bit user programmable OTP Cells - Figure 1. Package FBGA TFBGA88 (ZAQ) 8 x 10mm BLOCK LOCKING - All blocks locked at power-up - Any bination of blocks can be locked with zero latency - WPF for Block Lock-Down - Absolute Write Protection with VPPF = VSS - MON FLASH INTERFACE...