M48Z02 Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 READ mode . . . . . . . . . .
M48Z02 Key Features
- Integrated, ultra low power SRAM and powerfail control circuit
- Unlimited WRITE cycles
- READ cycle time equals WRITE cycle time
- Automatic power-fail chip deselect and WRITE protection
- WRITE protect voltages (VPFD = power-fail deselect voltage)
- Self-contained battery in the CAPHAT™ DIP package
- Pin and function patible with JEDEC standard 2 K x 8 SRAMs
- RoHS pliant
- Lead-free second level interconnect