M54HC4022 Datasheet | STMicroelectronics

M54HC4022 M74HC4022 OCTAL COUNTER/DIVIDER - . . . HIGH SPEED f MAX = 57 MHz (TYP.) at VCC = 5 V LOW POWER DISSIPATION ICC 4 µA (MAX.) at TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 m A (MIN.) BALANCED PROPAGATION DELAYS t PLH = t PHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V to 6 V PIN AND FUNCTION PATIBLE WITH 4022B B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC4022F1R M74HC4022M1R M74HC4022B1R M74HC4022C1R PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC4022 is a high speed CMOS OCTAL COUNTER/DIVIDER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL bined with true CMOS low power consumption. It contains a 4-stage divide-by-8 Johnson counter with 8 decoded outputs (Q0-Q7) and a Carry-out bit. This counter is advanced on the positive edge of the clock signal when CLOCK ENABLE input is held low, or is advanced on the negative edge of clock enable signal when CLOCK input is held high, and the selected one of eight outputs goes high. Holding the CLEAR input high clears the counter to zero regardless of the other input conditions. All inputs are equipped with protection circuits against static discharge and transient excess voltage. October 1992 NC = No Internal Connection 1/12 M54/M74HC4022 INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE CLOCK X L X CE X X H L L H H X: DON’T CARE CLEAR H L L L L L L DECODER OUTPUT (H) Q0 NO CHANGE NO CHANGE NO CHANGE + 1 NO CHANGE NO CHANGE NO CHANGE + 1 LOGIC DIAGRAM 2/12 M54/ M74HC4022 TIMING CHART PIN DESCRIPTION PIN No 3, 2, 4, 7, 10, 1, 5, 11 6, 9 12 13 14 15 8 16 SYMBOL Q0 to Q7 NC CARRY OUT CE CLOCK CLEAR GND V CC NAME AND FUNCTION Decoded Outputs Not Connected Carry Output (Active LOW) Clock Input (HIGH to LOW, Edge-triggered) Clock Input (LOW to HIGH, Edge-triggered) Master reset Input (Active...