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M616Z08-20MH3TR - 128 Kbit 8 Kbit x 16 SRAM WITH OUTPUT ENABLE

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M616Z08 128 Kbit (8 Kbit x 16) SRAM WITH OUTPUT ENABLE FEATURES SUMMARY s OPERATION VOLTAGE: 2.34V to 3.6V s s Figure 1. 44-pin, Hatless SOIC Package 8 Kbit x 16 SRAM EQUAL CYCLE and ACCESS TIMES: AS FAST AS 20ns TRI-STATE COMMON I/O TWO WRITE ENABLE PINS ALLOW WRITING TO UPPER AND LOWER BYTES 44 1 s s SO44 (MH) Figure 2. Logic Diagram VCC Table 1. Signal Names A0-A12 DQ0-DQ15 Address Inputs Data Input/Output Chip Enable Output Enable WRITE Enable DQ 0-7 WRITE Enable DQ 8-15 Supply Voltage Ground Time-Out Pin 13 A0-A12 16 DQ0-DQ15 CE OE WE0 WE0 WE1 M616Z08 WE1 TO CE OE VCC VSS TO VSS AI04213 Note: TO Pin should be connected to VCC. July 2002 1/14 M616Z08 TABLE OF CONTENTS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .