Click to expand full text
M68AF511A
4 Mbit (512K x8), 5V Asynchronous SRAM
FEATURES SUMMARY s SUPPLY VOLTAGE: 4.5 to 5.5V
s s s s s s
Figure 1. Packages
512K x 8 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 55ns LOW STANDBY CURRENT LOW VCC DATA RETENTION: 2V TRI-STATE COMMON I/O LOW ACTIVE and STANDBY POWER
TSOP32 Type II (NC)
32
1
SO32 (MC)
October 2002
1/18
M68AF511A
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Logic Diagram . . . . . . . . . . . . . . . Table 1. Signal Names . . . . . . . . . . . . . . . . Figure 3. TSOP and SO Connections . . . . . Figure 4. Block Diagram . . . . . . . . . . . . . . . ...................................... ..............................