Datasheet4U Logo Datasheet4U.com

M74HC240HV - OCTAL BUS BUFFER

Datasheet Summary

Description

The M54/74HC240HV and HC241HV are high speed CMOS OCTAL BUS BUFFERs fabricated in silicon gate C2MOS technology.

They have the same high speed performance of LSTTL combined with true CMOS low power consumption.

📥 Download Datasheet

Datasheet preview – M74HC240HV

Datasheet Details

Part number M74HC240HV
Manufacturer STMicroelectronics
File Size 210.03 KB
Description OCTAL BUS BUFFER
Datasheet download datasheet M74HC240HV Datasheet
Additional preview pages of the M74HC240HV datasheet.

📁 Similar Datasheet

  • M74HC253 - DUAL 4-CHANNEL MULTIPLEXER (STMicroelectronics)
  • M74HC00 - Quad 2 Input NAND Gate (SGS-Ates)
  • M74HC00 - Quad 2 Input NAND Gate (Mitsubishi)
  • M74HC109 - DUAL J-K FLIP FLOP (STMicroelectronics)
  • M74HC123 - DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR (STMicroelectronics)
  • M74HC125 - QUAD BUS BUFFER (STMicroelectronics)
  • M74HC125 - 3-STATE Quad Buffers (Fairchild Semiconductor)
  • M74HC126 - Quad bus buffer (STMicroelectronics)
  • M74HC148 - 8 TO 3 LINE PRIORITY ENCODER (STMicroelectronics)
  • M74HC151 - 8-channel multiplexer (STMicroelectronics)
Other Datasheets by ST Microelectronics

Full PDF Text Transcription

Click to expand full text
M54HC240HV/241HV M74HC240HV/241HV OCTAL BUS BUFFER WITH 3 STATE OUTPUTS HC240HV: INVERTED - HC241HV NON INVERTED . . . . . . . . HIGH SPEED tPD = 12 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION o ICC = 4 µA (MAX.) at TA = 25 C HIGH NOISE IMMUNITY VNIH = VINL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 6 mA (MIN) BALANCED PROPAGATION DELAYS tPLH = tPHL SAME FUNCTION OF HC240/241 PLUS HIGH TO LOW LEVEL LOGIC CONVERSION CAPABILITY LATCH UP FREE OPERATION ALSO WHEN VIH IS HIGHER THAN VCC B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) ORDER CODES : M54HCXXXHVF1R M74HCXXXHVM1R M74HCXXXHVB1R DESCRIPTION The M54/74HC240HV and HC241HV are high speed CMOS OCTAL BUS BUFFERs fabricated in silicon gate C2MOS technology.
Published: |