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SPEAR-09-H122 - SPEAr TM Head600

General Description

SPEAr Head600 is a powerful digital engine belonging to SPEAr family, the innovative customizable System on chip.

The device integrates an ARM 926 core with a large set of proven IPs and a big configurable logic block that allow very fast customization of unique and/or proprietary solution.

Key Features

  • ARM926EJ-S core @333MHz. 600KByte reconfigurable logic array with 88 dedicated General purposes I/Os, 9 LVDS channels and 128KByte configurable internal memory pool. Multilayer AMBA 2.0 compliant Bus with fMAX 166MHz 32KByte Rom. 8KByte common Static Ram. Dynamic Power saving features. High performance 8 channels DMA. Ethernet 10/100/1000 MAC with GMII/MII Interface to external PHY. USB2.0 device with integrated PHY. 2 USB2.0 Host with integrated PHY. Ext. SDRAM memory interface:.

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Full PDF Text Transcription for SPEAR-09-H122 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for SPEAR-09-H122. For precise diagrams, and layout, please refer to the original PDF.

www.DataSheet4U.com SPEAR-09-H122 SPEAr™ Head600 Preliminary Data Features ■ ■ ARM926EJ-S core @333MHz. 600KByte reconfigurable logic array with 88 dedicated General purp...

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Hz. 600KByte reconfigurable logic array with 88 dedicated General purposes I/Os, 9 LVDS channels and 128KByte configurable internal memory pool. Multilayer AMBA 2.0 compliant Bus with fMAX 166MHz 32KByte Rom. 8KByte common Static Ram. Dynamic Power saving features. High performance 8 channels DMA. Ethernet 10/100/1000 MAC with GMII/MII Interface to external PHY. USB2.0 device with integrated PHY. 2 USB2.0 Host with integrated PHY. Ext. SDRAM memory interface: – 8/16bit (DDR1@200MHz) – 8/16bit (DDR2@333MHz) Flashes interface: – Nand 8/16bit – Serial (up to 50Mbps). 3-SPI Master/Slave up to 40Mbps. I2C Master/Slave mode - Hi

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