ST5451 Datasheet | STMicroelectronics

DESCRIPTION ST5451 HDLC and GCI controller is a CMOS circuit fully developed by STMicroelectronics and diffused in advanced 1.2 µm HCMOS3 technology. The device is intended to be used mainly in ISDN applications, in Terminal (TE) and in Line Terminations (LT). ST5451 can handle HDLC packets either on 16Kbit/s D channel or 64 Kbit/s B channel; it can work with a wide range of PCM signals going from GCI (General Circuit Interface) to DSI (Digital System Interface) to any PCM-like stream. ST5451 is a plete GCI controller designed to ply with the GCI and GCI-SCIT (Special Circuit Interface for Terminal) pletely handling Monitor (M) and mand/Indicate (C/I) channels. ST5451 can be easily controlled by many different kind of microprocessors or microcontrollers having either non-multiplexed or multiplexed bus structure. ST5451 can be used in connection with ST5420/1 S Interface Devices (SID-µW and SID-GCI) and ST5080 Programmable ISDN bo (PIC) in Terminals and with ST5410 U Interface Device (UID) in Line Terminations. March 2000 1/34 is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without BLOCK DIAGRAM PIN DESCRIPTION NAME CS INT MULT I/M PIN 1 25 2 4 TYPE I O I I FUNCTION Chip Select. A low level enables ST5451 for read/write operations. Interrupt request is asserted by ST5451 when it request a service. Open drain output. Multiplexed Bus. Indicates the µP bus interface selected. MULT = 1: multiplexed bus and DMA available. MULT = 0: address and data bus separated. Intel/Motorola. When MULT = 1 this pin selects either Intel or Motorola 6805 bus. 2/34 DEMULTIPLEXED MICROPROCESSOR BUS INTERFACE (MULT = 0) NAME A0/A5 D0/D7 R/W E PIN 3-8 17-24 27 26 TYPE I I/O I I FUNCTION Address Bus. To transfer addresses from µP to ST5451. Data Bus. To transfer data between µP and ST5451. Read/Write. ”1” indicates a read operation; ”0” a write operation. Enable. Read/write operations are synchronized...