Datasheet Details
| Part number | STCCP27A |
|---|---|
| Manufacturer | STMicroelectronics |
| File Size | 305.18 KB |
| Description | High speed dual differential line receivers |
| Datasheet | STCCP27A_STMicroelectronics.pdf |
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Overview: www.DataSheet4U.com STCCP27A 1.8V/2.8V High speed dual differential line receivers, Compact camera port decoder, I2C control line Feature summary s SUB-Low voltage differential signaling inputs: VID = 100mV with RT = 100Ω, CL =10pF High signaling rate: fIN = 416MHz max (D+,D-, CLK+, CLK-) fOUT = 52MHz max (D1-D8, CLK) Very high speed: tpLH~tpHL=3.5ns (typ) at VDD=2.8V; VL=1.8V Operating voltage range: VDD(OPR) = 2.65V to 3.6V VL(OPR) =1.65V to 1.95V Symmetrical output impedance (D1-D8, H-SYNC, V-SYNC, CLK): IIOHI=IOL=8mA (min) at VDD=2.65V;VL=1.8V Low power dissipation (Disabled: EN=Gnd): ISOFF = IDD + IL = 10µA (max) CMOS logic input threshold (EN, SYNC_SEL): VIL = 0.3xVDD; VDD =2.65V to 3.6V VIH = 0.7xVDD; VDD =2.65V to 3.6V Bidirectional level translator line (I/OVDD, I/OVL) for I2C communications: 400kHz max frequency IIOHI= 20µA (min.) at VDD=2.8V;VL=1.8V IOL = 1 mA (min.) at VDD=2.8V;VL=1.8V 3.6V Tolerant on inputs (EN, SYNC_SEL) Leadfree µTFBGA package (RoHS restriction of hazardous substances) .
| Part number | STCCP27A |
|---|---|
| Manufacturer | STMicroelectronics |
| File Size | 305.18 KB |
| Description | High speed dual differential line receivers |
| Datasheet | STCCP27A_STMicroelectronics.pdf |
|
|
|
The STCCP27A receiver converts the subLVDS clock/datastream (up to 416 Mbps throughput bandwidth) back into parallel 8 bits of CMOS/ LVTTL.
The device recognizes the CCP 32bit start of frame (SOF), end of frame (EOF), start of line (SOL) and end of line (EOL) sequences to generate the H-SYNC and V-SYNC signals.
Output LVTTL clock (up to 52 MHz) is transmitted in parallel with data.
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