STCCP27A datasheet by STMicroelectronics.
| Part number | STCCP27A |
|---|---|
| Datasheet | STCCP27A_STMicroelectronics.pdf |
| File Size | 305.18 KB |
| Manufacturer | STMicroelectronics |
| Description | High speed dual differential line receivers |
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The STCCP27A receiver converts the subLVDS clock/datastream (up to 416 Mbps throughput bandwidth) back into parallel 8 bits of CMOS/ LVTTL. The device recognizes the CCP 32bit start of frame (SOF), end of frame (EOF), start of line (SOL) and end of line (EOL) sequences to generate the H-SYNC and V-SYNC signals. Output LVTTL clock (up to 52 MHz) is transmitted in parallel with data.
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