STLC2500 Description
The STLC2500 is a single chip ROM-based Bluetooth solution implemented in 0.13 m ultra low power, low leakage CMOS technology for applications requiring integration up to HCI level. Patch RAM is available enabling multiple patches/upgrades. The STLC2500's main interfaces are UART for HCI transport, PCM for voice and GPIOs for control purposes.
STLC2500 Key Features
- Improves speech quality in the vicinity of interference
- Improves coexistence with WLAN
- Works at receiver, no Bluetooth implication Adaptive Frequency Hopping (AFH): hopping kernel, channel assessment as Mast
- ACL: DM1, 3, 5 and DH1, 3, 5
- SCO: HV1, 3 and DV
- eSCO: EV3, 5 Clock support
- System clock input (digital or sine wave) at 13, 26, 19.2 or 38.4 MHz
- LPO clock input at 3.2, 16.384, 32 or 32.768 kHz ARM7TDMI CPU
- 32-bit Core
- AMBA (AHB-APB) bus configuration Patch RAM capability Memory organization