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STLC5466
64 CHANNEL-MULTI HDLC WITH N X 64KB/S SWITCHING MATRIX ASSOCIATED
PRELIMINARY DATA
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64 TX HDLCs with broadcasting capability and/ or CSMA/CR function with automatic restart in case of Tx frame abort 64 RX HDLCs including Address Recognition 16 Command/Indicate Channels (4 or 6-bit primitive) 16 Monitor Channels processed in accordance with GCI or V* 256 x 256 Switching Matrix without blocking and with Time Slot Sequence Integrity and loopback per bidirectional connection DMA Controller for 64 Tx Channels and 64 Rx Channels HDLCs AND DMA CONTROLLER ARE CAPABLE OF HANDLING A MIX OF LAPD,LAPB, SS7, CAS AND PROPRIETARY SIGNALLINGS External shared memory access between DMA Controller and Micro processor SINGLE MEMORY SHARED BETWEEN n x MUL