STR91xFA Description
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STR91xFA Key Features
- ARM966E-S RISC core: Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash)
- STR91xFA implementation of core adds high-speed burst Flash memory interface, instruction prefetch queue, branch cache
- Up to 96 MIPS directly from Flash memory
- Single-cycle DSP instructions are supported
- Binary patible with 16/32-bit ARM7 code
- Dual burst Flash memories, 32-bits wide
- 256KB/512KB Main Flash, 32KB 2nd Flash
- Sequential Burst operation up to 96 MHz
- 100K min erase cycles, 20 yr min retention
- SRAM, 32-bits wide