STU2071 Datasheet | STMicroelectronics

4B3T U INTERFACE CIRCUIT PRELIMINARY DATA 4B3T TWO-WIRE U INTERFACE CIRCUIT FOR LT AND NT APPLICATION 120 kbaud LINE SYMBOL RATE (120 SYMBOLS PER FRAME) SCRAMBLER AND DESCRAMBLER ACCORDING TO CCITT REC V.29 BARKER CODE (11 SYMBOLS) SYNCHRONIZATION WORD UNSCRAMBLED 1 KBIT/S HOUSEKEEPING CHANNEL ADAPTIVE ECHO CANCELLATION WITH TRANSVERSAL FILTERING ADAPTIVE DECISION FEEDBACK EQUALIZATION AUTOMATIC GAIN CONTROL PDM AD CONVERTER AUTOMATIC ACTIVATION AND DEACTIVATION WITH POLARITY ADAPTION AUTOMATIC CODE VIOLATION DETECTION POWER FEED UNIT CONTROL ADVANCED CL3 1.5µm CMOS PROCESS 28 PIN DUAL-IN-LINE PLASTIC PACKAGE V- DIGITAL INTERFACE DIP28 ORDERING NUMBER: STU2071B1 PLCC28 ORDERING NUMBER: STU2071FN SYSTEM OVERVIEW STU2071 (UIC) provides two transparent 64 kbit/s B channels, a transparent 16 kbit/s D channel, a transparent 1 kbit/s service channel and a 1 kbit/s maintenance channel for loop and error messages on subscriber lines. UIC enables full duplex continuous data transmission via the standard twisted pair telephone cable. Adaptive Echo cancellation is used to restore the received data. An equalizer, done with an adaptive filter, restores the data which are distorted by the transmission line. The coefficient of the equalizer and echo canceller are conserved during a power down. An all digital PLL performs both bit and frame synchronization. The analog front end consists of receive path RX and transmit path TX, providing a full duplex analog interfacing to the twisted pair telephone cable. Before data are converted to analog signals, they September 1994 pass through a digital filter (TX-filter) to reduce the high frequency ponents. After D/A conversion the signal is amplified and sent to the hybrid. The received signal is converted back to digital data and passed through the RX matching filter to restore the line signal. The A/D convertor is a second order sigma/delta modulator which operates with a clock of 15.36 MHz. After timing recovery,...