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72F521R9T6 - ST72F521R9T6

Datasheet Summary

Description

8 3 REGISTER & MEMORY MAP

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Features

  • ST72(F)521(M/R/AR)9 60K 2048 (256) TQFP64 14 x 14 TQFP80 14 x 14 TQFP64 10 x 10 s s and time base interrupt, external clock with event detector 4 Communications Interfaces.
  • SPI synchronous serial interface.
  • SCI asynchronous serial interface (LIN compatible).
  • I2C multimaster interface.
  • CAN interface (2.0B Passive) Analog peripheral.
  • 10-bit ADC with 16 input pins Instruction Set.
  • 8-bit Data Manipulation.
  • 63 Basic Instructions.

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ST72521M/R/AR 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE s s s s s Memories – 32K to 60K dual voltage High Density Flash (HDFlash) or ROM with read-out protection capability.
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