DESCRIPTION
making it flexible application. sub-micron silicon gate and double-layer metal All inputs and outputs are equipped with 2 wiring C MOS technology. TTL. It is composed of nine data inputs (A to I) and s HIGH SPEED: tPD = 4 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 280 IMPROVED LATCH-UP IMMUNITY B M (Plastic Package) (Micro Package) ORDER CODES : 74AC280B 74AC280M PIN CONNECTION AND IEC LOGIC SYMBOLS December 1998 1/8 74AC280 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 5, 6 8, 9, 10, 11, 12, 13, 1, 2, 4 3 7 14 SYMBOL ΣEVEN ΣODD A to I NAME AND FUNCT ION Parity Outputs Data Inputs NC GND VCC No Connection Ground (0V) Positive Supply Voltage TRUTH TABLE NUM...
STMicroelectronics
