DESCRIPTION
sub-micron silicon gate and double-layer metal 2 All inputs and outputs are equipped with wiring C MOS technology. TTL. These 8 bit D-Type flip-flops are controlled by a s HIGH SPEED: fMAX = 270 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 374 IMPROVED LATCH-UP IMMUNITY B M (Plastic Package) (Micro Package) ORDER CODES : 74AC374B 74AC374M PIN CONNECTION AND IEC LOGIC SYMBOLS April 1997 1/10 74AC374 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 SYMBOL OE Q0 to Q7 NAME AND F UNCTIO N 3 State Output Enable Input (Active LOW) 3 State Outputs D0 to D7 Data Inputs CLOCK GND VCC Clock Input (LOW to H...
STMicroelectronics
