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74AC573
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING
s s
s
s
s
s
latch enable input (LE) and an output enable input (OE). While the LE input is held at a high level, the Q s outputs will follow the data input precisely. When the LE is taken low, the Q outputs will be s latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be DESCRIPTION in a normal logic state (high or low logic level) The AC573 is an advanced high-speed CMOS www.DataSheet4U.com and while high level the outputs will be in a high OCTAL D-TYPE LATCH with 3 STATE OUTPUT impedance state.
74AC573 Datasheet
