DESCRIPTION
in a normal logic state (high or low logic level) NON INVERTING fabricated with sub-micron 2 All inputs and outputs are equipped with silicon gate and double-layer metal wiring C MOS protection circuits against static discharge, giving technology. equivalent Bipolar Schottky TTL. These 8 bit D-Type latches are controlled by a s HIGH SPEED: tPD = 4.5 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573 IMPROVED LATCH-UP IMMUNITY M B (Plastic Package) (Micro Package) ORDER CODES : 74AC573B 74AC573M PIN CONNECTION AND IEC LOGIC SYMBOLS April 1997 1/10 74AC573 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2, 3, 4, 5, 6, 7, 8, 9 12, 13, 14, 15, 16, 17, 18, 19 11 10...
STMicroelectronics
