DESCRIPTION
impedance state. wiring C2MOS technology. All inputs and outputs are equipped with These 8 bit D-Type flip-flops are controlled by a protection circuits against static discharge, giving clock input (CK) and an output enable input (OE). them 2KV ESD immunity and transient excess voltage. On the positive transition of the clock, the Q PIN CONNECTION AND IEC LOGIC SYMBOLS HIGH SPEED: fMAX = 220 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 574 IMPROVED LATCH-UP IMMUNITY DIP PACKAGE DIP SOP TSSOP SOP ORDER CODES T UBE M74AC574B M74AC574M TSSOP T& R M74AC574MTR M74AC574TTR February 2000 1/11 74AC574 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2, 3, 4, 5, 6, 7...
STMicroelectronics
